;buildInfoPackage: chisel3, version: 3.4.3, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit top : 
  module count_clk : 
    input clock : Clock
    input reset : Reset
    output io : {Data_in : UInt<1>, count_clk_in : UInt<10>, count_clk_delay : UInt<10>, count_clk_enable : UInt<10>, count_clk_out : UInt<10>, flip Data : UInt<210>, flip stateReg : UInt<3>}
    
    reg count_clk_in : UInt<10>, clock with : (reset => (reset, UInt<10>("h00"))) @[PUF_Core.scala 145:36]
    reg count_clk_delay : UInt<10>, clock with : (reset => (reset, UInt<10>("h00"))) @[PUF_Core.scala 146:36]
    reg count_clk_enable : UInt<10>, clock with : (reset => (reset, UInt<10>("h00"))) @[PUF_Core.scala 147:36]
    reg count_clk_out : UInt<10>, clock with : (reset => (reset, UInt<10>("h00"))) @[PUF_Core.scala 148:36]
    wire the_data_in : UInt<1> @[PUF_Core.scala 149:33]
    node _the_data_in_T = dshr(io.Data, count_clk_in) @[PUF_Core.scala 151:35]
    node _the_data_in_T_1 = bits(_the_data_in_T, 0, 0) @[PUF_Core.scala 151:52]
    the_data_in <= _the_data_in_T_1 @[PUF_Core.scala 151:21]
    node _T = eq(io.stateReg, UInt<3>("h01")) @[PUF_Core.scala 155:23]
    when _T : @[PUF_Core.scala 155:36]
      node _count_clk_in_T = add(count_clk_in, UInt<1>("h01")) @[PUF_Core.scala 156:42]
      node _count_clk_in_T_1 = tail(_count_clk_in_T, 1) @[PUF_Core.scala 156:42]
      count_clk_in <= _count_clk_in_T_1 @[PUF_Core.scala 156:25]
      skip @[PUF_Core.scala 155:36]
    else : @[PUF_Core.scala 157:16]
      count_clk_in <= UInt<1>("h00") @[PUF_Core.scala 158:25]
      skip @[PUF_Core.scala 157:16]
    node _T_1 = eq(io.stateReg, UInt<3>("h02")) @[PUF_Core.scala 161:23]
    when _T_1 : @[PUF_Core.scala 161:36]
      node _count_clk_delay_T = add(count_clk_delay, UInt<1>("h01")) @[PUF_Core.scala 162:45]
      node _count_clk_delay_T_1 = tail(_count_clk_delay_T, 1) @[PUF_Core.scala 162:45]
      count_clk_delay <= _count_clk_delay_T_1 @[PUF_Core.scala 162:25]
      skip @[PUF_Core.scala 161:36]
    else : @[PUF_Core.scala 164:15]
      count_clk_delay <= UInt<1>("h00") @[PUF_Core.scala 165:25]
      skip @[PUF_Core.scala 164:15]
    node _T_2 = eq(io.stateReg, UInt<3>("h03")) @[PUF_Core.scala 168:23]
    when _T_2 : @[PUF_Core.scala 168:37]
      node _count_clk_enable_T = add(count_clk_enable, UInt<1>("h01")) @[PUF_Core.scala 169:50]
      node _count_clk_enable_T_1 = tail(_count_clk_enable_T, 1) @[PUF_Core.scala 169:50]
      count_clk_enable <= _count_clk_enable_T_1 @[PUF_Core.scala 169:29]
      skip @[PUF_Core.scala 168:37]
    else : @[PUF_Core.scala 171:15]
      count_clk_enable <= UInt<1>("h00") @[PUF_Core.scala 172:29]
      skip @[PUF_Core.scala 171:15]
    node _T_3 = eq(io.stateReg, UInt<3>("h04")) @[PUF_Core.scala 175:23]
    when _T_3 : @[PUF_Core.scala 175:37]
      node _count_clk_out_T = add(count_clk_out, UInt<1>("h01")) @[PUF_Core.scala 176:43]
      node _count_clk_out_T_1 = tail(_count_clk_out_T, 1) @[PUF_Core.scala 176:43]
      count_clk_out <= _count_clk_out_T_1 @[PUF_Core.scala 176:25]
      skip @[PUF_Core.scala 175:37]
    else : @[PUF_Core.scala 178:15]
      count_clk_out <= UInt<1>("h00") @[PUF_Core.scala 179:25]
      skip @[PUF_Core.scala 178:15]
    io.Data_in <= the_data_in @[PUF_Core.scala 182:25]
    io.count_clk_in <= count_clk_in @[PUF_Core.scala 183:25]
    io.count_clk_delay <= count_clk_delay @[PUF_Core.scala 184:25]
    io.count_clk_enable <= count_clk_enable @[PUF_Core.scala 185:25]
    io.count_clk_out <= count_clk_out @[PUF_Core.scala 186:25]
    
  module puf_core : 
    input clock : Clock
    input reset : Reset
    output io : {out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>}, ctr : {flip puf_in_valid : UInt<1>, puf_in_ready : UInt<1>, flip puf_data_in : UInt<210>, puf_out_valid : UInt<1>, flip puf_out_ready : UInt<1>, flip puf_wl_ena : UInt<1>, flip puf_write_ena : UInt<1>}, clk : {flip Clk : Clock}}
    
    wire the_ena_in : UInt<1> @[PUF_Core.scala 18:33]
    reg the_ena_out : UInt<1>, clock @[PUF_Core.scala 19:32]
    wire the_clk_in : UInt<1> @[PUF_Core.scala 20:33]
    wire the_clk_out : UInt<1> @[PUF_Core.scala 21:33]
    wire the_data_in : UInt<1> @[PUF_Core.scala 22:33]
    wire count_clk_in : UInt<10>
    count_clk_in <= UInt<10>("h00")
    wire count_clk_delay : UInt<10>
    count_clk_delay <= UInt<10>("h00")
    wire count_clk_enable : UInt<10>
    count_clk_enable <= UInt<10>("h00")
    wire count_clk_out : UInt<10>
    count_clk_out <= UInt<10>("h00")
    wire trigger_input : UInt<1> @[PUF_Core.scala 29:33]
    wire trigger_delay : UInt<1> @[PUF_Core.scala 30:33]
    wire trigger_enable : UInt<1> @[PUF_Core.scala 31:33]
    wire trigger_output : UInt<1> @[PUF_Core.scala 32:33]
    wire trigger_idle : UInt<1> @[PUF_Core.scala 33:33]
    reg stateReg : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[PUF_Core.scala 37:40]
    inst M_Count_Clk of count_clk @[PUF_Core.scala 39:39]
    M_Count_Clk.clock <= clock
    M_Count_Clk.reset <= reset
    io.out.Data_in <= the_data_in @[PUF_Core.scala 43:25]
    io.out.Ena_in <= the_ena_in @[PUF_Core.scala 44:25]
    reg io_out_Ena_out_REG : UInt<1>, clock @[PUF_Core.scala 45:36]
    io_out_Ena_out_REG <= the_ena_out @[PUF_Core.scala 45:36]
    io.out.Ena_out <= io_out_Ena_out_REG @[PUF_Core.scala 45:25]
    io.out.Clk_in <= the_clk_in @[PUF_Core.scala 46:25]
    io.out.Clk_out <= the_clk_out @[PUF_Core.scala 47:25]
    M_Count_Clk.clock <= io.clk.Clk @[PUF_Core.scala 49:29]
    M_Count_Clk.io.Data <= io.ctr.puf_data_in @[PUF_Core.scala 50:29]
    M_Count_Clk.io.stateReg <= stateReg @[PUF_Core.scala 51:29]
    count_clk_in <= M_Count_Clk.io.count_clk_in @[PUF_Core.scala 52:29]
    count_clk_delay <= M_Count_Clk.io.count_clk_delay @[PUF_Core.scala 53:29]
    count_clk_enable <= M_Count_Clk.io.count_clk_enable @[PUF_Core.scala 54:29]
    count_clk_out <= M_Count_Clk.io.count_clk_out @[PUF_Core.scala 55:29]
    the_data_in <= M_Count_Clk.io.Data_in @[PUF_Core.scala 56:29]
    io.ctr.puf_in_ready <= trigger_delay @[PUF_Core.scala 62:29]
    node _io_ctr_puf_out_valid_T = not(the_clk_out) @[PUF_Core.scala 63:50]
    node _io_ctr_puf_out_valid_T_1 = and(trigger_idle, _io_ctr_puf_out_valid_T) @[PUF_Core.scala 63:46]
    io.ctr.puf_out_valid <= _io_ctr_puf_out_valid_T_1 @[PUF_Core.scala 63:29]
    trigger_input <= io.ctr.puf_in_valid @[PUF_Core.scala 66:25]
    node _trigger_delay_T = eq(count_clk_in, UInt<8>("h0d2")) @[PUF_Core.scala 67:49]
    trigger_delay <= _trigger_delay_T @[PUF_Core.scala 67:25]
    node _trigger_enable_T = eq(count_clk_delay, UInt<3>("h04")) @[PUF_Core.scala 68:49]
    trigger_enable <= _trigger_enable_T @[PUF_Core.scala 68:25]
    node _trigger_output_T = eq(count_clk_enable, UInt<2>("h02")) @[PUF_Core.scala 69:49]
    trigger_output <= _trigger_output_T @[PUF_Core.scala 69:25]
    node _trigger_idle_T = sub(UInt<8>("h080"), UInt<2>("h02")) @[PUF_Core.scala 70:65]
    node _trigger_idle_T_1 = tail(_trigger_idle_T, 1) @[PUF_Core.scala 70:65]
    node _trigger_idle_T_2 = eq(count_clk_out, _trigger_idle_T_1) @[PUF_Core.scala 70:49]
    trigger_idle <= _trigger_idle_T_2 @[PUF_Core.scala 70:25]
    node _T = eq(stateReg, UInt<3>("h01")) @[PUF_Core.scala 73:20]
    when _T : @[PUF_Core.scala 73:33]
      the_ena_in <= UInt<1>("h00") @[PUF_Core.scala 74:25]
      the_ena_out <= UInt<1>("h00") @[PUF_Core.scala 75:25]
      the_clk_in <= UInt<1>("h01") @[PUF_Core.scala 76:25]
      the_clk_out <= UInt<1>("h00") @[PUF_Core.scala 77:25]
      skip @[PUF_Core.scala 73:33]
    else : @[PUF_Core.scala 79:38]
      node _T_1 = eq(stateReg, UInt<3>("h02")) @[PUF_Core.scala 79:25]
      when _T_1 : @[PUF_Core.scala 79:38]
        the_ena_in <= UInt<1>("h01") @[PUF_Core.scala 80:25]
        the_ena_out <= UInt<1>("h00") @[PUF_Core.scala 81:25]
        the_clk_in <= UInt<1>("h00") @[PUF_Core.scala 82:25]
        the_clk_out <= UInt<1>("h00") @[PUF_Core.scala 83:25]
        skip @[PUF_Core.scala 79:38]
      else : @[PUF_Core.scala 85:39]
        node _T_2 = eq(stateReg, UInt<3>("h03")) @[PUF_Core.scala 85:25]
        when _T_2 : @[PUF_Core.scala 85:39]
          the_ena_in <= UInt<1>("h01") @[PUF_Core.scala 86:25]
          the_ena_out <= UInt<1>("h01") @[PUF_Core.scala 87:25]
          the_clk_in <= UInt<1>("h00") @[PUF_Core.scala 88:25]
          the_clk_out <= UInt<1>("h01") @[PUF_Core.scala 89:25]
          skip @[PUF_Core.scala 85:39]
        else : @[PUF_Core.scala 91:39]
          node _T_3 = eq(stateReg, UInt<3>("h04")) @[PUF_Core.scala 91:25]
          when _T_3 : @[PUF_Core.scala 91:39]
            the_ena_in <= UInt<1>("h00") @[PUF_Core.scala 92:25]
            the_ena_out <= UInt<1>("h01") @[PUF_Core.scala 93:25]
            the_clk_in <= UInt<1>("h01") @[PUF_Core.scala 94:25]
            the_clk_out <= UInt<1>("h01") @[PUF_Core.scala 95:25]
            skip @[PUF_Core.scala 91:39]
          else : @[PUF_Core.scala 97:15]
            the_ena_in <= UInt<1>("h00") @[PUF_Core.scala 98:25]
            the_ena_out <= UInt<1>("h00") @[PUF_Core.scala 99:25]
            the_clk_in <= UInt<1>("h00") @[PUF_Core.scala 100:25]
            the_clk_out <= UInt<1>("h00") @[PUF_Core.scala 101:25]
            skip @[PUF_Core.scala 97:15]
    node _T_4 = eq(stateReg, UInt<3>("h01")) @[PUF_Core.scala 105:20]
    when _T_4 : @[PUF_Core.scala 105:33]
      when trigger_delay : @[PUF_Core.scala 106:31]
        stateReg <= UInt<3>("h02") @[PUF_Core.scala 107:25]
        skip @[PUF_Core.scala 106:31]
      skip @[PUF_Core.scala 105:33]
    else : @[PUF_Core.scala 110:38]
      node _T_5 = eq(stateReg, UInt<3>("h02")) @[PUF_Core.scala 110:25]
      when _T_5 : @[PUF_Core.scala 110:38]
        when trigger_enable : @[PUF_Core.scala 111:31]
          stateReg <= UInt<3>("h03") @[PUF_Core.scala 112:25]
          skip @[PUF_Core.scala 111:31]
        skip @[PUF_Core.scala 110:38]
      else : @[PUF_Core.scala 115:38]
        node _T_6 = eq(stateReg, UInt<3>("h03")) @[PUF_Core.scala 115:25]
        when _T_6 : @[PUF_Core.scala 115:38]
          when trigger_output : @[PUF_Core.scala 116:32]
            stateReg <= UInt<3>("h04") @[PUF_Core.scala 117:25]
            skip @[PUF_Core.scala 116:32]
          skip @[PUF_Core.scala 115:38]
        else : @[PUF_Core.scala 120:38]
          node _T_7 = eq(stateReg, UInt<3>("h04")) @[PUF_Core.scala 120:25]
          when _T_7 : @[PUF_Core.scala 120:38]
            when trigger_idle : @[PUF_Core.scala 121:30]
              stateReg <= UInt<3>("h00") @[PUF_Core.scala 122:25]
              skip @[PUF_Core.scala 121:30]
            skip @[PUF_Core.scala 120:38]
          else : @[PUF_Core.scala 125:16]
            when trigger_input : @[PUF_Core.scala 126:31]
              stateReg <= UInt<3>("h01") @[PUF_Core.scala 127:25]
              skip @[PUF_Core.scala 126:31]
            skip @[PUF_Core.scala 125:16]
    
  module read_data : 
    input clock : Clock
    input reset : Reset
    output io : {flip ena : UInt<1>, flip channel : UInt<1>, output : UInt<128>}
    
    reg result : UInt<128>, clock with : (reset => (reset, UInt<128>("h00"))) @[PUF_Top.scala 90:32]
    reg count : UInt<10>, clock with : (reset => (reset, UInt<10>("h00"))) @[PUF_Top.scala 91:32]
    when io.ena : @[PUF_Top.scala 93:19]
      node _count_T = add(count, UInt<1>("h01")) @[PUF_Top.scala 94:35]
      node _count_T_1 = tail(_count_T, 1) @[PUF_Top.scala 94:35]
      count <= _count_T_1 @[PUF_Top.scala 94:25]
      skip @[PUF_Top.scala 93:19]
    else : @[PUF_Top.scala 95:16]
      count <= UInt<1>("h00") @[PUF_Top.scala 96:25]
      skip @[PUF_Top.scala 95:16]
    node _T = sub(UInt<8>("h080"), UInt<1>("h01")) @[PUF_Top.scala 100:43]
    node _T_1 = tail(_T, 1) @[PUF_Top.scala 100:43]
    node _T_2 = lt(count, _T_1) @[PUF_Top.scala 100:29]
    node _T_3 = and(io.ena, _T_2) @[PUF_Top.scala 100:18]
    when _T_3 : @[PUF_Top.scala 100:51]
      node result_lo = bits(result, 127, 1) @[PUF_Top.scala 102:44]
      node _result_T = cat(io.channel, result_lo) @[Cat.scala 30:58]
      result <= _result_T @[PUF_Top.scala 102:17]
      skip @[PUF_Top.scala 100:51]
    io.output <= result @[PUF_Top.scala 105:21]
    
  module Clk_Divider2 : 
    input clock : Clock
    input reset : Reset
    output io : {clk_out : Clock}
    
    reg the_clk : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Clk_Divider2.scala 12:28]
    node _the_clk_T = not(the_clk) @[Clk_Divider2.scala 13:21]
    the_clk <= _the_clk_T @[Clk_Divider2.scala 13:17]
    node _io_clk_out_T = asClock(the_clk) @[Clk_Divider2.scala 15:29]
    io.clk_out <= _io_clk_out_T @[Clk_Divider2.scala 15:17]
    
  module puf_subtop : 
    input clock : Clock
    input reset : Reset
    output io : {out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, flip Data_out : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>, Clk : UInt<1>, WL_Enable : UInt<1>, Write_Ena : UInt<1>}, ctr : {flip puf_in_valid : UInt<1>, puf_in_ready : UInt<1>, flip puf_data_in : UInt<210>, puf_out_valid : UInt<1>, flip puf_out_ready : UInt<1>, puf_data_out : UInt<128>, flip puf_wl_ena : UInt<1>, flip puf_write_ena : UInt<1>}}
    
    inst M_PUF_Core of puf_core @[PUF_Top.scala 39:35]
    M_PUF_Core.clock <= clock
    M_PUF_Core.reset <= reset
    inst M_read_data of read_data @[PUF_Top.scala 40:35]
    M_read_data.clock <= clock
    M_read_data.reset <= reset
    inst the_clock_M_Clk_Divider of Clk_Divider2 @[Clk_Divider2.scala 21:35]
    the_clock_M_Clk_Divider.clock <= clock
    the_clock_M_Clk_Divider.reset <= reset
    wire the_clock_reverse : Clock @[PUF_Top.scala 43:37]
    node _the_clock_reverse_T = asUInt(the_clock_M_Clk_Divider.io.clk_out) @[PUF_Top.scala 44:47]
    node _the_clock_reverse_T_1 = bits(_the_clock_reverse_T, 0, 0) @[PUF_Top.scala 44:47]
    node _the_clock_reverse_T_2 = mux(_the_clock_reverse_T_1, UInt<1>("h00"), UInt<1>("h01")) @[PUF_Top.scala 44:36]
    node _the_clock_reverse_T_3 = asClock(_the_clock_reverse_T_2) @[PUF_Top.scala 44:72]
    the_clock_reverse <= _the_clock_reverse_T_3 @[PUF_Top.scala 44:29]
    M_PUF_Core.io.clk.Clk <= the_clock_reverse @[PUF_Top.scala 47:37]
    M_read_data.clock <= the_clock_M_Clk_Divider.io.clk_out @[PUF_Top.scala 50:29]
    reg M_read_data_io_ena_REG : UInt<1>, clock @[PUF_Top.scala 51:40]
    M_read_data_io_ena_REG <= M_PUF_Core.io.out.Ena_out @[PUF_Top.scala 51:40]
    M_read_data.io.ena <= M_read_data_io_ena_REG @[PUF_Top.scala 51:29]
    M_read_data.io.channel <= io.out.Data_out @[PUF_Top.scala 52:29]
    reg the_ena_in : UInt<1>, clock @[PUF_Top.scala 54:40]
    the_ena_in <= M_PUF_Core.io.out.Ena_in @[PUF_Top.scala 54:40]
    node the_wl_enable = mux(io.ctr.puf_wl_ena, the_ena_in, UInt<1>("h00")) @[PUF_Top.scala 55:36]
    node the_write_ena = mux(io.ctr.puf_write_ena, the_ena_in, UInt<1>("h00")) @[PUF_Top.scala 56:36]
    reg io_out_Data_in_REG : UInt, clock @[PUF_Top.scala 58:40]
    io_out_Data_in_REG <= M_PUF_Core.io.out.Data_in @[PUF_Top.scala 58:40]
    io.out.Data_in <= io_out_Data_in_REG @[PUF_Top.scala 58:29]
    io.out.Ena_in <= the_ena_in @[PUF_Top.scala 59:29]
    reg io_out_Ena_out_REG : UInt<1>, clock @[PUF_Top.scala 60:40]
    io_out_Ena_out_REG <= M_PUF_Core.io.out.Ena_out @[PUF_Top.scala 60:40]
    io.out.Ena_out <= io_out_Ena_out_REG @[PUF_Top.scala 60:29]
    node _io_out_Clk_in_T = asUInt(the_clock_M_Clk_Divider.io.clk_out) @[PUF_Top.scala 61:79]
    node _io_out_Clk_in_T_1 = bits(_io_out_Clk_in_T, 0, 0) @[PUF_Top.scala 61:86]
    node _io_out_Clk_in_T_2 = and(M_PUF_Core.io.out.Clk_in, _io_out_Clk_in_T_1) @[PUF_Top.scala 61:66]
    reg io_out_Clk_in_REG : UInt<1>, clock @[PUF_Top.scala 61:40]
    io_out_Clk_in_REG <= _io_out_Clk_in_T_2 @[PUF_Top.scala 61:40]
    io.out.Clk_in <= io_out_Clk_in_REG @[PUF_Top.scala 61:29]
    node _io_out_Clk_out_T = asUInt(the_clock_reverse) @[PUF_Top.scala 62:88]
    node _io_out_Clk_out_T_1 = bits(_io_out_Clk_out_T, 0, 0) @[PUF_Top.scala 62:95]
    node _io_out_Clk_out_T_2 = and(M_PUF_Core.io.out.Clk_out, _io_out_Clk_out_T_1) @[PUF_Top.scala 62:67]
    reg io_out_Clk_out_REG : UInt<1>, clock @[PUF_Top.scala 62:40]
    io_out_Clk_out_REG <= _io_out_Clk_out_T_2 @[PUF_Top.scala 62:40]
    io.out.Clk_out <= io_out_Clk_out_REG @[PUF_Top.scala 62:29]
    reg io_out_Clk_REG : UInt<1>, clock @[PUF_Top.scala 65:40]
    io_out_Clk_REG <= the_ena_in @[PUF_Top.scala 65:40]
    io.out.Clk <= io_out_Clk_REG @[PUF_Top.scala 65:29]
    reg io_out_WL_Enable_REG : UInt<1>, clock @[PUF_Top.scala 66:40]
    io_out_WL_Enable_REG <= the_wl_enable @[PUF_Top.scala 66:40]
    io.out.WL_Enable <= io_out_WL_Enable_REG @[PUF_Top.scala 66:29]
    reg io_out_Write_Ena_REG : UInt<1>, clock @[PUF_Top.scala 67:40]
    io_out_Write_Ena_REG <= the_write_ena @[PUF_Top.scala 67:40]
    io.out.Write_Ena <= io_out_Write_Ena_REG @[PUF_Top.scala 67:29]
    M_PUF_Core.io.ctr.puf_in_valid <= io.ctr.puf_in_valid @[PUF_Top.scala 69:37]
    io.ctr.puf_in_ready <= M_PUF_Core.io.ctr.puf_in_ready @[PUF_Top.scala 70:37]
    M_PUF_Core.io.ctr.puf_data_in <= io.ctr.puf_data_in @[PUF_Top.scala 71:37]
    io.ctr.puf_out_valid <= M_PUF_Core.io.ctr.puf_out_valid @[PUF_Top.scala 73:37]
    M_PUF_Core.io.ctr.puf_out_ready <= io.ctr.puf_out_ready @[PUF_Top.scala 74:37]
    io.ctr.puf_data_out <= M_read_data.io.output @[PUF_Top.scala 75:37]
    M_PUF_Core.io.ctr.puf_wl_ena <= io.ctr.puf_wl_ena @[PUF_Top.scala 77:37]
    M_PUF_Core.io.ctr.puf_write_ena <= io.ctr.puf_write_ena @[PUF_Top.scala 78:37]
    
  extmodule clk_divider : 
    input clk : Clock
    input rst_p : UInt<1>
    output clk_div : Clock
    
    defname = clk_divider
    parameter NUM_DIV = 100
    parameter CNT_LEN = 8
    
  module puf_top : 
    input clock : Clock
    input reset : Reset
    output io : {out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, flip Data_out : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>, Clk : UInt<1>, WL_Enable : UInt<1>, Write_Ena : UInt<1>}, ctr : {flip puf_in_valid : UInt<1>, puf_in_ready : UInt<1>, flip puf_data_in : UInt<210>, puf_out_valid : UInt<1>, flip puf_out_ready : UInt<1>, puf_data_out : UInt<128>, flip puf_wl_ena : UInt<1>, flip puf_write_ena : UInt<1>}}
    
    inst M_PUF_SubTop of puf_subtop @[PUF_Top.scala 19:35]
    M_PUF_SubTop.clock <= clock
    M_PUF_SubTop.reset <= reset
    inst M_Clk_Divider of clk_divider @[PUF_Top.scala 20:35]
    M_Clk_Divider.clk_div is invalid
    M_Clk_Divider.rst_p is invalid
    M_Clk_Divider.clk is invalid
    wire the_clock : Clock @[PUF_Top.scala 22:33]
    M_Clk_Divider.clk <= clock @[PUF_Top.scala 23:29]
    node _M_Clk_Divider_io_rst_p_T = asUInt(reset) @[PUF_Top.scala 24:39]
    M_Clk_Divider.rst_p <= _M_Clk_Divider_io_rst_p_T @[PUF_Top.scala 24:29]
    the_clock <= M_Clk_Divider.clk_div @[PUF_Top.scala 25:29]
    M_PUF_SubTop.clock <= the_clock @[PUF_Top.scala 27:29]
    io.out.Write_Ena <= M_PUF_SubTop.io.out.Write_Ena @[PUF_Top.scala 28:29]
    io.out.WL_Enable <= M_PUF_SubTop.io.out.WL_Enable @[PUF_Top.scala 28:29]
    io.out.Clk <= M_PUF_SubTop.io.out.Clk @[PUF_Top.scala 28:29]
    io.out.Clk_out <= M_PUF_SubTop.io.out.Clk_out @[PUF_Top.scala 28:29]
    io.out.Ena_out <= M_PUF_SubTop.io.out.Ena_out @[PUF_Top.scala 28:29]
    M_PUF_SubTop.io.out.Data_out <= io.out.Data_out @[PUF_Top.scala 28:29]
    io.out.Clk_in <= M_PUF_SubTop.io.out.Clk_in @[PUF_Top.scala 28:29]
    io.out.Ena_in <= M_PUF_SubTop.io.out.Ena_in @[PUF_Top.scala 28:29]
    io.out.Data_in <= M_PUF_SubTop.io.out.Data_in @[PUF_Top.scala 28:29]
    M_PUF_SubTop.io.ctr.puf_write_ena <= io.ctr.puf_write_ena @[PUF_Top.scala 29:29]
    M_PUF_SubTop.io.ctr.puf_wl_ena <= io.ctr.puf_wl_ena @[PUF_Top.scala 29:29]
    io.ctr.puf_data_out <= M_PUF_SubTop.io.ctr.puf_data_out @[PUF_Top.scala 29:29]
    M_PUF_SubTop.io.ctr.puf_out_ready <= io.ctr.puf_out_ready @[PUF_Top.scala 29:29]
    io.ctr.puf_out_valid <= M_PUF_SubTop.io.ctr.puf_out_valid @[PUF_Top.scala 29:29]
    M_PUF_SubTop.io.ctr.puf_data_in <= io.ctr.puf_data_in @[PUF_Top.scala 29:29]
    io.ctr.puf_in_ready <= M_PUF_SubTop.io.ctr.puf_in_ready @[PUF_Top.scala 29:29]
    M_PUF_SubTop.io.ctr.puf_in_valid <= io.ctr.puf_in_valid @[PUF_Top.scala 29:29]
    
  module control : 
    input clock : Clock
    input reset : Reset
    output io : {flip uart_tx_ready : UInt<1>, uart_tx_valid : UInt<1>, uart_tx_data : UInt<8>, flip uart_rx_data : UInt<8>, flip uart_rx_valid : UInt<1>, uart_rx_ready : UInt<1>, puf_in_valid : UInt<1>, flip puf_in_ready : UInt<1>, puf_data_in : UInt<210>, flip puf_out_valid : UInt<1>, puf_out_ready : UInt<1>, flip puf_data_out : UInt<128>, puf_wl_ena : UInt<1>, puf_write_ena : UInt<1>, led : UInt<8>}
    
    reg data_control : UInt<8>, clock with : (reset => (reset, UInt<8>("h00"))) @[control.scala 45:40]
    wire _data_stimulus_WIRE : UInt<8>[27] @[control.scala 46:48]
    _data_stimulus_WIRE[0] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[1] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[2] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[3] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[4] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[5] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[6] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[7] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[8] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[9] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[10] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[11] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[12] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[13] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[14] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[15] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[16] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[17] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[18] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[19] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[20] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[21] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[22] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[23] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[24] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[25] <= UInt<8>("h00") @[control.scala 46:48]
    _data_stimulus_WIRE[26] <= UInt<8>("h00") @[control.scala 46:48]
    reg data_stimulus : UInt<8>[27], clock with : (reset => (reset, _data_stimulus_WIRE)) @[control.scala 46:40]
    wire _data_output_WIRE : UInt<8>[16] @[control.scala 47:48]
    _data_output_WIRE[0] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[1] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[2] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[3] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[4] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[5] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[6] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[7] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[8] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[9] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[10] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[11] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[12] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[13] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[14] <= UInt<8>("h00") @[control.scala 47:48]
    _data_output_WIRE[15] <= UInt<8>("h00") @[control.scala 47:48]
    reg data_output : UInt<8>[16], clock with : (reset => (reset, _data_output_WIRE)) @[control.scala 47:40]
    io.led <= data_control @[control.scala 50:29]
    reg cnt_input : UInt<10>, clock @[control.scala 52:36]
    reg cnt_output : UInt<10>, clock @[control.scala 53:36]
    wire trigger_receive : UInt<1> @[control.scala 55:37]
    wire trigger_pufin : UInt<1> @[control.scala 56:37]
    wire trigger_pufout : UInt<1> @[control.scala 57:37]
    wire trigger_send : UInt<1> @[control.scala 58:37]
    wire trigger_done : UInt<1> @[control.scala 59:37]
    reg stateReg : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[control.scala 63:32]
    node _T = eq(io.uart_rx_data, UInt<7>("h053")) @[control.scala 73:48]
    node _T_1 = and(io.uart_rx_valid, _T) @[control.scala 73:28]
    when _T_1 : @[control.scala 73:62]
      trigger_receive <= UInt<1>("h01") @[control.scala 74:29]
      skip @[control.scala 73:62]
    else : @[control.scala 75:16]
      trigger_receive <= UInt<1>("h00") @[control.scala 76:29]
      skip @[control.scala 75:16]
    node _T_2 = eq(cnt_input, UInt<5>("h01c")) @[control.scala 79:21]
    when _T_2 : @[control.scala 79:41]
      trigger_pufin <= UInt<1>("h01") @[control.scala 80:29]
      skip @[control.scala 79:41]
    else : @[control.scala 81:16]
      trigger_pufin <= UInt<1>("h00") @[control.scala 82:29]
      skip @[control.scala 81:16]
    when io.puf_in_ready : @[control.scala 85:28]
      trigger_pufout <= UInt<1>("h01") @[control.scala 86:29]
      skip @[control.scala 85:28]
    else : @[control.scala 87:16]
      trigger_pufout <= UInt<1>("h00") @[control.scala 88:28]
      skip @[control.scala 87:16]
    when io.puf_out_valid : @[control.scala 91:29]
      trigger_send <= UInt<1>("h01") @[control.scala 92:29]
      skip @[control.scala 91:29]
    else : @[control.scala 93:16]
      trigger_send <= UInt<1>("h00") @[control.scala 94:29]
      skip @[control.scala 93:16]
    node _T_3 = sub(UInt<5>("h010"), UInt<1>("h01")) @[control.scala 97:40]
    node _T_4 = tail(_T_3, 1) @[control.scala 97:40]
    node _T_5 = eq(cnt_output, _T_4) @[control.scala 97:22]
    when _T_5 : @[control.scala 97:46]
      trigger_done <= UInt<1>("h01") @[control.scala 98:29]
      skip @[control.scala 97:46]
    else : @[control.scala 99:16]
      trigger_done <= UInt<1>("h00") @[control.scala 100:29]
      skip @[control.scala 99:16]
    node _T_6 = eq(stateReg, UInt<3>("h00")) @[control.scala 110:20]
    when _T_6 : @[control.scala 110:31]
      when trigger_receive : @[control.scala 111:32]
        stateReg <= UInt<3>("h01") @[control.scala 112:25]
        skip @[control.scala 111:32]
      skip @[control.scala 110:31]
    else : @[control.scala 115:38]
      node _T_7 = eq(stateReg, UInt<3>("h01")) @[control.scala 115:25]
      when _T_7 : @[control.scala 115:38]
        when trigger_pufin : @[control.scala 116:30]
          stateReg <= UInt<3>("h02") @[control.scala 117:25]
          skip @[control.scala 116:30]
        skip @[control.scala 115:38]
      else : @[control.scala 120:37]
        node _T_8 = eq(stateReg, UInt<3>("h02")) @[control.scala 120:25]
        when _T_8 : @[control.scala 120:37]
          when trigger_pufout : @[control.scala 121:31]
            stateReg <= UInt<3>("h03") @[control.scala 122:25]
            skip @[control.scala 121:31]
          skip @[control.scala 120:37]
        else : @[control.scala 125:38]
          node _T_9 = eq(stateReg, UInt<3>("h03")) @[control.scala 125:25]
          when _T_9 : @[control.scala 125:38]
            when trigger_send : @[control.scala 126:29]
              stateReg <= UInt<3>("h04") @[control.scala 127:25]
              skip @[control.scala 126:29]
            skip @[control.scala 125:38]
          else : @[control.scala 130:36]
            node _T_10 = eq(stateReg, UInt<3>("h04")) @[control.scala 130:25]
            when _T_10 : @[control.scala 130:36]
              when trigger_done : @[control.scala 131:29]
                stateReg <= UInt<3>("h00") @[control.scala 132:25]
                skip @[control.scala 131:29]
              skip @[control.scala 130:36]
    io.uart_rx_ready <= UInt<1>("h01") @[control.scala 143:25]
    node _T_11 = eq(stateReg, UInt<3>("h01")) @[control.scala 145:20]
    when _T_11 : @[control.scala 145:33]
      when io.uart_rx_valid : @[control.scala 146:33]
        node _T_12 = lt(cnt_input, UInt<5>("h01b")) @[control.scala 147:29]
        when _T_12 : @[control.scala 147:50]
          node _T_13 = bits(cnt_input, 4, 0)
          data_stimulus[_T_13] <= io.uart_rx_data @[control.scala 148:49]
          skip @[control.scala 147:50]
        else : @[control.scala 150:57]
          node _T_14 = eq(cnt_input, UInt<5>("h01b")) @[control.scala 150:34]
          when _T_14 : @[control.scala 150:57]
            data_control <= io.uart_rx_data @[control.scala 151:33]
            skip @[control.scala 150:57]
        node _cnt_input_T = add(cnt_input, UInt<1>("h01")) @[control.scala 154:59]
        node _cnt_input_T_1 = tail(_cnt_input_T, 1) @[control.scala 154:59]
        cnt_input <= _cnt_input_T_1 @[control.scala 154:45]
        skip @[control.scala 146:33]
      skip @[control.scala 145:33]
    else : @[control.scala 156:16]
      cnt_input <= UInt<1>("h00") @[control.scala 157:21]
      skip @[control.scala 156:16]
    node _T_15 = eq(stateReg, UInt<3>("h02")) @[control.scala 161:20]
    when _T_15 : @[control.scala 161:32]
      io.puf_in_valid <= UInt<1>("h01") @[control.scala 162:25]
      node io_puf_data_in_lo_lo_lo_hi = cat(data_stimulus[2], data_stimulus[1]) @[control.scala 165:43]
      node io_puf_data_in_lo_lo_lo = cat(io_puf_data_in_lo_lo_lo_hi, data_stimulus[0]) @[control.scala 165:43]
      node io_puf_data_in_lo_lo_hi_hi = cat(data_stimulus[5], data_stimulus[4]) @[control.scala 165:43]
      node io_puf_data_in_lo_lo_hi = cat(io_puf_data_in_lo_lo_hi_hi, data_stimulus[3]) @[control.scala 165:43]
      node io_puf_data_in_lo_lo = cat(io_puf_data_in_lo_lo_hi, io_puf_data_in_lo_lo_lo) @[control.scala 165:43]
      node io_puf_data_in_lo_hi_lo_hi = cat(data_stimulus[8], data_stimulus[7]) @[control.scala 165:43]
      node io_puf_data_in_lo_hi_lo = cat(io_puf_data_in_lo_hi_lo_hi, data_stimulus[6]) @[control.scala 165:43]
      node io_puf_data_in_lo_hi_hi_lo = cat(data_stimulus[10], data_stimulus[9]) @[control.scala 165:43]
      node io_puf_data_in_lo_hi_hi_hi = cat(data_stimulus[12], data_stimulus[11]) @[control.scala 165:43]
      node io_puf_data_in_lo_hi_hi = cat(io_puf_data_in_lo_hi_hi_hi, io_puf_data_in_lo_hi_hi_lo) @[control.scala 165:43]
      node io_puf_data_in_lo_hi = cat(io_puf_data_in_lo_hi_hi, io_puf_data_in_lo_hi_lo) @[control.scala 165:43]
      node io_puf_data_in_lo = cat(io_puf_data_in_lo_hi, io_puf_data_in_lo_lo) @[control.scala 165:43]
      node io_puf_data_in_hi_lo_lo_hi = cat(data_stimulus[15], data_stimulus[14]) @[control.scala 165:43]
      node io_puf_data_in_hi_lo_lo = cat(io_puf_data_in_hi_lo_lo_hi, data_stimulus[13]) @[control.scala 165:43]
      node io_puf_data_in_hi_lo_hi_lo = cat(data_stimulus[17], data_stimulus[16]) @[control.scala 165:43]
      node io_puf_data_in_hi_lo_hi_hi = cat(data_stimulus[19], data_stimulus[18]) @[control.scala 165:43]
      node io_puf_data_in_hi_lo_hi = cat(io_puf_data_in_hi_lo_hi_hi, io_puf_data_in_hi_lo_hi_lo) @[control.scala 165:43]
      node io_puf_data_in_hi_lo = cat(io_puf_data_in_hi_lo_hi, io_puf_data_in_hi_lo_lo) @[control.scala 165:43]
      node io_puf_data_in_hi_hi_lo_hi = cat(data_stimulus[22], data_stimulus[21]) @[control.scala 165:43]
      node io_puf_data_in_hi_hi_lo = cat(io_puf_data_in_hi_hi_lo_hi, data_stimulus[20]) @[control.scala 165:43]
      node io_puf_data_in_hi_hi_hi_lo = cat(data_stimulus[24], data_stimulus[23]) @[control.scala 165:43]
      node io_puf_data_in_hi_hi_hi_hi = cat(data_stimulus[26], data_stimulus[25]) @[control.scala 165:43]
      node io_puf_data_in_hi_hi_hi = cat(io_puf_data_in_hi_hi_hi_hi, io_puf_data_in_hi_hi_hi_lo) @[control.scala 165:43]
      node io_puf_data_in_hi_hi = cat(io_puf_data_in_hi_hi_hi, io_puf_data_in_hi_hi_lo) @[control.scala 165:43]
      node io_puf_data_in_hi = cat(io_puf_data_in_hi_hi, io_puf_data_in_hi_lo) @[control.scala 165:43]
      node _io_puf_data_in_T = cat(io_puf_data_in_hi, io_puf_data_in_lo) @[control.scala 165:43]
      io.puf_data_in <= _io_puf_data_in_T @[control.scala 165:25]
      skip @[control.scala 161:32]
    else : @[control.scala 166:16]
      io.puf_in_valid <= UInt<1>("h00") @[control.scala 167:25]
      io.puf_data_in <= UInt<1>("h00") @[control.scala 168:25]
      skip @[control.scala 166:16]
    node _T_16 = eq(stateReg, UInt<3>("h03")) @[control.scala 177:20]
    when _T_16 : @[control.scala 177:33]
      io.puf_out_ready <= UInt<1>("h01") @[control.scala 178:29]
      node _io_puf_wl_ena_T = bits(data_control, 3, 0) @[control.scala 182:49]
      node _io_puf_wl_ena_T_1 = eq(_io_puf_wl_ena_T, UInt<4>("h0f")) @[control.scala 182:55]
      io.puf_wl_ena <= _io_puf_wl_ena_T_1 @[control.scala 182:33]
      node _io_puf_write_ena_T = bits(data_control, 7, 4) @[control.scala 183:49]
      node _io_puf_write_ena_T_1 = eq(_io_puf_write_ena_T, UInt<4>("h0f")) @[control.scala 183:55]
      io.puf_write_ena <= _io_puf_write_ena_T_1 @[control.scala 183:33]
      when io.puf_out_valid : @[control.scala 185:33]
        node _data_output_0_T = bits(io.puf_data_out, 7, 0) @[control.scala 187:50]
        data_output[0] <= _data_output_0_T @[control.scala 187:32]
        node _data_output_1_T = bits(io.puf_data_out, 15, 8) @[control.scala 187:50]
        data_output[1] <= _data_output_1_T @[control.scala 187:32]
        node _data_output_2_T = bits(io.puf_data_out, 23, 16) @[control.scala 187:50]
        data_output[2] <= _data_output_2_T @[control.scala 187:32]
        node _data_output_3_T = bits(io.puf_data_out, 31, 24) @[control.scala 187:50]
        data_output[3] <= _data_output_3_T @[control.scala 187:32]
        node _data_output_4_T = bits(io.puf_data_out, 39, 32) @[control.scala 187:50]
        data_output[4] <= _data_output_4_T @[control.scala 187:32]
        node _data_output_5_T = bits(io.puf_data_out, 47, 40) @[control.scala 187:50]
        data_output[5] <= _data_output_5_T @[control.scala 187:32]
        node _data_output_6_T = bits(io.puf_data_out, 55, 48) @[control.scala 187:50]
        data_output[6] <= _data_output_6_T @[control.scala 187:32]
        node _data_output_7_T = bits(io.puf_data_out, 63, 56) @[control.scala 187:50]
        data_output[7] <= _data_output_7_T @[control.scala 187:32]
        node _data_output_8_T = bits(io.puf_data_out, 71, 64) @[control.scala 187:50]
        data_output[8] <= _data_output_8_T @[control.scala 187:32]
        node _data_output_9_T = bits(io.puf_data_out, 79, 72) @[control.scala 187:50]
        data_output[9] <= _data_output_9_T @[control.scala 187:32]
        node _data_output_10_T = bits(io.puf_data_out, 87, 80) @[control.scala 187:50]
        data_output[10] <= _data_output_10_T @[control.scala 187:32]
        node _data_output_11_T = bits(io.puf_data_out, 95, 88) @[control.scala 187:50]
        data_output[11] <= _data_output_11_T @[control.scala 187:32]
        node _data_output_12_T = bits(io.puf_data_out, 103, 96) @[control.scala 187:50]
        data_output[12] <= _data_output_12_T @[control.scala 187:32]
        node _data_output_13_T = bits(io.puf_data_out, 111, 104) @[control.scala 187:50]
        data_output[13] <= _data_output_13_T @[control.scala 187:32]
        node _data_output_14_T = bits(io.puf_data_out, 119, 112) @[control.scala 187:50]
        data_output[14] <= _data_output_14_T @[control.scala 187:32]
        node _data_output_15_T = bits(io.puf_data_out, 127, 120) @[control.scala 187:50]
        data_output[15] <= _data_output_15_T @[control.scala 187:32]
        skip @[control.scala 185:33]
      skip @[control.scala 177:33]
    else : @[control.scala 198:16]
      io.puf_out_ready <= UInt<1>("h00") @[control.scala 199:29]
      io.puf_wl_ena <= UInt<1>("h00") @[control.scala 201:29]
      io.puf_write_ena <= UInt<1>("h00") @[control.scala 202:29]
      skip @[control.scala 198:16]
    node _T_17 = eq(stateReg, UInt<3>("h04")) @[control.scala 205:20]
    when _T_17 : @[control.scala 205:31]
      io.uart_tx_valid <= UInt<1>("h01") @[control.scala 206:29]
      when io.uart_tx_ready : @[control.scala 207:33]
        node _io_uart_tx_data_T = bits(cnt_output, 3, 0)
        io.uart_tx_data <= data_output[_io_uart_tx_data_T] @[control.scala 208:29]
        node _cnt_output_T = add(cnt_output, UInt<1>("h01")) @[control.scala 209:44]
        node _cnt_output_T_1 = tail(_cnt_output_T, 1) @[control.scala 209:44]
        cnt_output <= _cnt_output_T_1 @[control.scala 209:29]
        skip @[control.scala 207:33]
      else : @[control.scala 210:20]
        io.uart_tx_data <= UInt<1>("h00") @[control.scala 211:29]
        skip @[control.scala 210:20]
      skip @[control.scala 205:31]
    else : @[control.scala 213:16]
      io.uart_tx_data <= UInt<1>("h00") @[control.scala 214:29]
      io.uart_tx_valid <= UInt<1>("h00") @[control.scala 215:29]
      cnt_output <= UInt<1>("h00") @[control.scala 216:29]
      skip @[control.scala 213:16]
    
  extmodule uart_tx : 
    input clk : Clock
    input rst_n : Reset
    input tx_data : UInt<8>
    input tx_data_valid : UInt<1>
    output tx_data_ready : UInt<1>
    output tx_pin : UInt<1>
    
    defname = uart_tx
    parameter CLK_FRE = 100
    parameter BAUD_RATE = 115200
    
  extmodule uart_rx : 
    input clk : Clock
    input rst_n : Reset
    input rx_data_ready : UInt<1>
    input rx_pin : UInt<1>
    output rx_data : UInt<8>
    output rx_data_valid : UInt<1>
    
    defname = uart_rx
    parameter CLK_FRE = 100
    parameter BAUD_RATE = 115200
    
  extmodule clk_divider_1 : 
    input clk : Clock
    input rst_p : UInt<1>
    output clk_div : Clock
    
    defname = clk_divider
    parameter NUM_DIV = 100
    parameter CNT_LEN = 8
    
  module top : 
    input clock : Clock
    input reset : UInt<1>
    output io : {led : {led : UInt<8>}, test_out : UInt<1>, uart : {flip uart_rx : UInt<1>, uart_tx : UInt<1>}, puf_out : {Data_in : UInt<1>, Ena_in : UInt<1>, Clk_in : UInt<1>, flip Data_out : UInt<1>, Ena_out : UInt<1>, Clk_out : UInt<1>, Clk : UInt<1>, WL_Enable : UInt<1>, Write_Ena : UInt<1>}}
    
    inst M_puf of puf_top @[top.scala 19:35]
    M_puf.clock <= clock
    M_puf.reset <= reset
    inst M_control of control @[top.scala 20:35]
    M_control.clock <= clock
    M_control.reset <= reset
    inst M_uart_tx of uart_tx @[top.scala 21:35]
    M_uart_tx.tx_pin is invalid
    M_uart_tx.tx_data_ready is invalid
    M_uart_tx.tx_data_valid is invalid
    M_uart_tx.tx_data is invalid
    M_uart_tx.rst_n is invalid
    M_uart_tx.clk is invalid
    inst M_uart_rx of uart_rx @[top.scala 22:35]
    M_uart_rx.rx_data_valid is invalid
    M_uart_rx.rx_data is invalid
    M_uart_rx.rx_pin is invalid
    M_uart_rx.rx_data_ready is invalid
    M_uart_rx.rst_n is invalid
    M_uart_rx.clk is invalid
    wire rst_n : Reset @[top.scala 24:33]
    node _rst_n_T = bits(reset, 0, 0) @[top.scala 25:39]
    node _rst_n_T_1 = mux(_rst_n_T, UInt<1>("h00"), UInt<1>("h01")) @[top.scala 25:32]
    rst_n <= _rst_n_T_1 @[top.scala 25:25]
    io.led.led <= M_control.io.led @[top.scala 34:25]
    inst M_Clk_Divider of clk_divider_1 @[top.scala 35:35]
    M_Clk_Divider.clk_div is invalid
    M_Clk_Divider.rst_p is invalid
    M_Clk_Divider.clk is invalid
    node _M_Clk_Divider_io_clk_T = asClock(io.puf_out.Clk_out) @[top.scala 36:52]
    M_Clk_Divider.clk <= _M_Clk_Divider_io_clk_T @[top.scala 36:29]
    node _M_Clk_Divider_io_rst_p_T = bits(reset, 0, 0) @[top.scala 37:39]
    M_Clk_Divider.rst_p <= _M_Clk_Divider_io_rst_p_T @[top.scala 37:29]
    node _io_test_out_T = asUInt(M_Clk_Divider.clk_div) @[top.scala 38:58]
    node _io_test_out_T_1 = bits(_io_test_out_T, 0, 0) @[top.scala 38:58]
    io.test_out <= _io_test_out_T_1 @[top.scala 38:29]
    M_uart_tx.clk <= clock @[top.scala 48:33]
    M_uart_tx.rst_n <= rst_n @[top.scala 49:33]
    M_uart_tx.tx_data <= M_control.io.uart_tx_data @[top.scala 50:33]
    M_uart_tx.tx_data_valid <= M_control.io.uart_tx_valid @[top.scala 51:33]
    M_control.io.uart_tx_ready <= M_uart_tx.tx_data_ready @[top.scala 53:33]
    io.uart.uart_tx <= M_uart_tx.tx_pin @[top.scala 54:33]
    M_uart_rx.clk <= clock @[top.scala 64:33]
    M_uart_rx.rst_n <= rst_n @[top.scala 65:33]
    M_uart_rx.rx_data_ready <= M_control.io.uart_rx_ready @[top.scala 66:33]
    M_uart_rx.rx_pin <= io.uart.uart_rx @[top.scala 67:33]
    M_control.io.uart_rx_data <= M_uart_rx.rx_data @[top.scala 69:33]
    M_control.io.uart_rx_valid <= M_uart_rx.rx_data_valid @[top.scala 70:33]
    io.puf_out.Write_Ena <= M_puf.io.out.Write_Ena @[top.scala 79:33]
    io.puf_out.WL_Enable <= M_puf.io.out.WL_Enable @[top.scala 79:33]
    io.puf_out.Clk <= M_puf.io.out.Clk @[top.scala 79:33]
    io.puf_out.Clk_out <= M_puf.io.out.Clk_out @[top.scala 79:33]
    io.puf_out.Ena_out <= M_puf.io.out.Ena_out @[top.scala 79:33]
    M_puf.io.out.Data_out <= io.puf_out.Data_out @[top.scala 79:33]
    io.puf_out.Clk_in <= M_puf.io.out.Clk_in @[top.scala 79:33]
    io.puf_out.Ena_in <= M_puf.io.out.Ena_in @[top.scala 79:33]
    io.puf_out.Data_in <= M_puf.io.out.Data_in @[top.scala 79:33]
    M_puf.io.ctr.puf_in_valid <= M_control.io.puf_in_valid @[top.scala 80:33]
    M_puf.io.ctr.puf_data_in <= M_control.io.puf_data_in @[top.scala 81:33]
    M_puf.io.ctr.puf_out_ready <= M_control.io.puf_out_ready @[top.scala 82:33]
    M_puf.io.ctr.puf_wl_ena <= M_control.io.puf_wl_ena @[top.scala 83:33]
    M_puf.io.ctr.puf_write_ena <= M_control.io.puf_write_ena @[top.scala 84:33]
    M_control.io.puf_in_ready <= M_puf.io.ctr.puf_in_ready @[top.scala 86:33]
    M_control.io.puf_out_valid <= M_puf.io.ctr.puf_out_valid @[top.scala 87:33]
    M_control.io.puf_data_out <= M_puf.io.ctr.puf_data_out @[top.scala 88:33]
    
